在移植u-boot的过程看到过u-boot在重定向时的实现,当时不知道怎么就觉得很好理解就把这个知识点没怎么深入的理解,最近在看华为的鸿蒙OS在Cortex-A平台上的实现过程时再次遇到一时间看不太懂了,所以花了点时间研究了一下这里做一下记录,后续有时间再把u-boot的实现再复盘一下加深理解。具体的代码如下
1 /*
2 * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * 'AS IS' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #define ASSEMBLY
33 #include 'arch_config.h'
34 #include 'los_vm_boot.h'
35 #include 'los_vm_zone.h'
36 #include 'los_mmu_descriptor_v6.h'
37 #undef ASSEMBLY
38
39
40 .global __exc_stack_top
41 .global __irq_stack_top
42 .global __fiq_stack_top
43 .global __svc_stack_top
44 .global __abt_stack_top
45 .global __undef_stack_top
46 .global __exc_stack
47 .global __irq_stack
48 .global __fiq_stack
49 .global __svc_stack
50 .global __abt_stack
51 .global __undef_stack
52
53 .extern __bss_start
54 .extern __bss_end
55 .extern hal_clock_initialize_start
56 .extern los_bss_init
57 .extern _osExceptFiqHdl
58 .extern _osExceptAddrAbortHdl
59 .extern _osExceptDataAbortHdl
60 .extern _osExceptPrefetchAbortHdl
61 .extern _osExceptSwiHdl
62 .extern _osExceptUndefInstrHdl
63 .extern __stack_chk_guard_setup
64 .extern g_firstPageTable
65 .extern g_mmuJumpPageTable
66
67 .equ MPIDR_CPUID_MASK, 0xffU
68
69 .fpu vfpv4
70 .arm
71
72 /* param0 is stack bottom, param1 is stack size, r11 hold cpu id */
73 .macro EXC_SP_SET param0, param1
74 ldr r1, =param0
75 mov r0, param1
76 bl sp_set
77 .endm
78
79 /* param0 is stack top, param1 is stack size, param2 is magic num */
80 .macro STACK_MAGIC_SET param0, param1, param2
81 ldr r0, =param0
82 mov r1, param1
83 ldr r2, =param2
84 bl excstack_magic
85 .endm
86
87 /* param0 is physical address, param1 virtual address, param2 is sizes, param3 is flag */
88 .macro PAGE_TABLE_SET param0, param1, param2, param3
89 ldr r6, =param0
90 ldr r7, =param1
91 ldr r8, =param2
92 ldr r10, =param3
93 bl page_table_build
94 .endm
95 .code 32
96 .section '.vectors','ax'
97
98 __exception_handlers:
99 /*
100 *Assumption: ROM code has these vectors at the hardware reset address.
101 *A simple jump removes any address-space dependencies [i.e. safer]
102 */
103 b reset_vector
104 b _osExceptUndefInstrHdl
105 b _osExceptSwiHdl
106 b _osExceptPrefetchAbortHdl
107 b _osExceptDataAbortHdl
108 b _osExceptAddrAbortHdl
109 b OsIrqHandler
110 b _osExceptFiqHdl
111
112 /* Startup code which will get the machine into supervisor mode */
113 .global reset_vector
114 .type reset_vector,function
115 reset_vector:
116 /* do some early cpu setup: i/d cache disable, mmu disabled */
117 mrc p15, 0, r0, c1, c0, 0
118 bic r0, #(1<<12)
119 bic r0, #(1<<2 | 1<<0)
120 mcr p15, 0, r0, c1, c0, 0
121
122 /* r11: delta of physical address and virtual address */
123 adr r11, pa_va_offset;此时r11为物理地址 具体原因是硬件决定了第一条指令的地址,当执行到这里pc此时是当前的指令的地址(自然是物理地址)
124 ;然后而adr伪指令的作用就是得到了当前标识pa_va_offset和当前指令的offset和保存在r11,而代码的实现在这个标识处定
125 ;义了一个连接地址相关的标识'.'所以按照程序连接指定的运行地址(虚拟的)这里保存的值肯定是连接实际的虚拟运行地址所以r0为虚拟地址
126 ldr r0, [r11]
127 sub r11, r11, r0 ;进而物理地址减去虚拟地址(连接地址)即就是物理地址和虚拟地址的差。
128
129 /* if we need to relocate to proper location or not */
130 adr r4, __exception_handlers /* r4: base of load address */
131 ldr r5, =SYS_MEM_BASE /* r5: base of physical address */
132 subs r12, r4, r5 /* r12: delta of load address and physical address */
133 beq reloc_img_to_bottom_done /* if we load image at the bottom of physical address */
134
135 /* we need to relocate image at the bottom of physical address */
136 ldr r7, =__exception_handlers /* r7: base of linked address (or vm address) */
137 ldr r6, =__bss_start /* r6: end of linked address (or vm address) */
138 sub r6, r7 /* r6: delta of linked address (or vm address) */
139 add r6, r4 /* r6: end of load address */
140
141 reloc_img_to_bottom_loop:
142 ldr r7, [r4], #4
143 str r7, [r5], #4
144 cmp r4, r6
145 bne reloc_img_to_bottom_loop
146 sub pc, r12
147 nop
148 sub r11, r11, r12 /* r11: eventual address offset */
149
150 reloc_img_to_bottom_done:
151 ldr r4, =g_firstPageTable /* r4: physical address of translation table and clear it */
152 add r4, r4, r11
153 bl page_table_clear
154
155 PAGE_TABLE_SET SYS_MEM_BASE, KERNEL_VMM_BASE, KERNEL_VMM_SIZE, MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS
156 PAGE_TABLE_SET SYS_MEM_BASE, UNCACHED_VMM_BASE, UNCACHED_VMM_SIZE, MMU_INITIAL_MAP_STRONGLY_ORDERED
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现代雷达系统的信号设计
BFR340T






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