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1. Direct and oversee all aspects of the GPU datacenter business development functions for China/Asian datacenter customers
2. Understand customer h/w and s/w requirements, configurations, applications and architect solutions accordingly on GPU data Center
3. Cultivate, nurture and maintain relationships with key personnel within the customer organization
4. Participate as a member of business development team in sharing market/customer knowledge and insights, as well as collaborate with customer regarding joint strategic direction and priorities.
5. Ensure proper communications to sales and product departments regarding changes in our customer business needs and expectations.
PMTS/SMTS/MTS/Sr Machine/ Deep Learning Software engineer
2.Should have expertise in: ICC2, Primetime, Calibre.
3.Expertise in Perl and Tcl is a must
4.Must have good communication & Analytical thinking skills
2.Focus on block synthesis to sign off timing and improve synthesis netlist quality
3.Work with PD tile owners to improve place's QoR
2.Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
3.Familiar with unix/linux and scripts (tcl, perl etc.)
2.Expertise in UVM based verification methodology
3.Proficiency in System Verilog, C or C++
4.Expertise in Perl, Tcl or other scripting language
5.Knowledge of graphics architecture is a plus
2.Computer architecture and computer arithmetic
3.Computer graphics basic knowledge
4.Experience with database technologies and database-driven custom web application development
5.Familiar with Unix/Linux and scripts (TCL, Ruby, Perl, Python etc.)
2.Solid skill of of C/C++ programming
3.Solid experience of Linux kernel or Linux device driver development
4.Deep Knowledge of Computer Architecture and Computer Graphics
5.Deep Knowledge of x86 assembler language and x86/x64 CPU instructions
2. 2. Knowledge of Linux /Server Structure
3. Experience in Co-work with internal R&D team
4. Solid skill in Software/Machine learning background
1. Work on next generation OpenGL/Vulkan technologies
2. Work on support for next generation Microsoft Windows, Linux and Android operating system
3. Maintain current driver and improve performance
1. Validation leader responsible for CPU, Graphic, Chipset, Memory and system features. Systems are integrated combinations of hardware components (CPUs, graphics, memory, IO adapters, peripherals) and software components (firmware, drivers, OS, virtualization, and system management). This individual will interface with the Marketing, Silicon design, Software and Hardware design, SEL/LSE and Validation teams to define our validation strategy and drive validation execution for new silicon and platforms, and provide detailed technical direction to the validation engineers.
2.For SMU design, drive RTL implementation, for SMN design, drive netwrok topology design to achieve best performance/latency for a given SOC floorplan
3.Collaborate with verification, feint, PD, software, platform team from an end-to-end ownership perspective
4.Support silicon bring-up and issue triage
1.familiar with Linux/C/C++
2.have knowledge on RTL.
3.Fluent in English
2. Good knowledge of systemverilog and UVM verification
3. Familiar with linux environment, skillful at script languages like perl, ruby, C shell, Makefile
2.Provide and drive the platform solution by leading the related design teams
3.Provide the technical guidance to customer support team
4.Drive innovation to optimize the designs
2.Very knowledgeable on the x86 platform architecture and Strong familiarity with graphics architecture is a plus
3.Familiar with the interface industry standards specifications is a plus
1. Bachelor’s or master’s degree in Computer Science or related field with at least 10 years’ Software Engineering experience and 5 years’ Management experience
2. Experience in relevant technology, including 3D graphics, CPU/GPU driver development, GPGPU, or Machine Learning
3. C/C++ programming background in the Linux environment
2. Strong experience on C/C++/Matlab, Proficient in algorithms of video/image processing
3. Experience on camera /ISP software, firmware or algorithm design is preferred
2. 8+ years industry experience with low level software development in C/C++
3. Experience with operating system development, low-level device driver or embedded driver development strongly preferred and knowledge of GPU and CPU architectures
2. Strong programming skills in C or C++ and scripting language (Python, Perl ) knowledge and UNIX/Linux experience is required
3. GPU programming experience in OpenCL, CUDA, HIP, or similar; practical experience optimizing a GPU-accelerated program
2. Proven skill on x86/ARM assembly and C/C++ language, demonstrable C/C++ programming skills
3. Solid experience with Kernel mode driver programming under Linux/Android OS and solid knowledge on AOSP/Linux Kernel/Linux V4L2 architecture
1. Expert of Verilog RTL design and has experience of large digital ASIC project.
2. Familiar with front-end EDA tools and flows.
3. Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
2. Must be proficient in Verilog and System Verilog language
3. Must be good at C/C++ programming, and working in Linux and Windows environments
1. Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
2. Have hands-on experience in Chiplevel Design/Integration activities.
3. Expertise in Perl and Tcl is a plus
SMTS ASIC/Layout Design Engineer
2. Co-Work with archtitecture design team and give feedback and propose on architecture improvement.
3. Lead real workload based performance verification, evaluation and analysis for new chip
2. Strong background in computer architecture, parallel processing and/or high performance computing
3. Big plus with Computer Graphics, CPU, or Driver Experience
1. Some Physical Design exposure required.
2. Some exposure to DFT is a strong plus.
3. Expertise in script (Perl, Tcl) is a must.
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Design and implement other DFX (debug, characterization, yield etc) logics
8. 4+ years hands on working experience on ASIC DFT design and verification
2. Build C/C++ model for simulation
3. Build test bench and monitors for DUT
4. Compose test plan and validation vectors to ensure functional completeness
5. Debug function/performance bugs of graphics IP
6. Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
7. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc
8. Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
1. Image, signal processing, Mathematics and related area education background
2. Solid knowledge in mathematics and physics and expert in using mathematical method to resolve image processing problem
3. Expert in ISP pipeline architecture and principles and expert in one of below areas: HDR, noise reduction, color space, de-mosaic, edge enhancement or 3A
1. Mastered at least one of the listed programming languages: C/C++, Java, Python, Matlab
2. Above 1 year’s software development experience under Windows/Linux
3. Strong analysis and problem solving skills, fast learner on new technical area
1. Proven skill on C/C++/Python
2. Solid experience with OpenCV//OpenCL/Matlab/CUDA or other framework and languages
3. 3+ year experience in Computer Vision development, familiar with Tensorflow, Caffe , Mxnet and ONNX is a plus
2.Experience in physical design of deep submicron digital ASIC chips
3.Successfully gone through several complete product development cycles
1. Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area, rich experience of complex ASIC DV flow from plan to coverage
2. Sincere interests in AI/HPC GPU projects
3. Knowledgeable in C++ & SV, familiar with script languages like Ruby/Perl/Makefile…
2.Proficient debugging skill
3.In-depth knowledge on software engineering and design pattern
4.Ability to learn new techniques and features
2. Familiar with low-power design
3. Familiar with Front-End or Back-End EDA tools
1. Prefer experience with Verigy ATE test development
2. Prefer experience with ATPG Scan, Memory BIST, Crest Functional test or HSIO test
3. Thorough understanding of device physics and semiconductor Fab processing for advance technology nodes below 40nm.