电路简单双打输入频率-Simple Circuit Doub

2011-05-26 18:18:27来源: 互联网
Abstract: A simple circuit consisting of a comparator and an exclusive-OR gate is sufficient to double the frequency of a reference signal.

The versatile phase-locked loop (PLL) allows multiplication of a reference frequency with an operating frequency that ranges from "DC to daylight." A PLL is overkill for some applications, however, especially if the input frequency needs only to be doubled. For those cases a simpler approach—such as the circuit in Figure 1 — will do the job just as well.


Figure 1. This circuit doubles the input frequency.

The reference frequency in this circuit drives the input of an exclusive-OR gate (XOR gate U2) as well as the input to a delay circuit. Consisting of R1, C1, and comparator U1, the delay circuit drives the XOR gate's second input. A resistive divider from the power supply establishes a 50% threshold for the delay circuit (2.5V in this case).

Circuit operation is easily illustrated by its response to a discrete pulse. If the input is low for a long time, pin 4 of the XOR gate is low but pin 5 is high, due to signal inversion by the comparator. The XOR output is therefore high. If the pin-4 input is now driven high, the XOR gate responds immediately by driving its output low. But after the delay circuit responds (about 15ns in this case), the XOR output returns high. Thus, a single rising edge on the input causes a single negative pulse at the XOR output. In a similar manner, the system produces a single pulse in response to an input falling edge. The resulting output (Figure 2) doubles an input frequency from 15MHz to 30MHz.


Figure 2. The Figure 1 circuit doubles a 15MHz input frequency+ to 30MHz.

A few simple selections configure this circuit for an application. The logic gate must operate from the desired supply voltage and provide adequate speed for the application. The delay components, R1 and C1, are determined by the equation

where fDOUBLE is the desired (doubled) output frequency. At higher frequencies R1 should be in the 1k range, but its value can be increased at lower frequencies. The calculated values of R1 and C1 may need adjustment to compensate for propagation delay in the comparator. Choosing a fast comparator (such as the MAX9010) helps to alleviate this concern. For low-level signals the MAX9010 propagation delay is 5ns, but a high level of overdrive in this application makes it faster than 5ns.

The circuit is useful in systems for which a clock frequency is already present, but other circuitry requires a higher frequency. Using a doubler instead of a second clock oscillator prevents the beat frequencies that might otherwise occur.

This design idea appeared in the December 15, 2003 issue of EE Times magazine.

关键字:输入  频率

编辑:神话 引用地址:http://www.eeworld.com.cn/mndz/2011/0526/article_9182.html
本网站转载的所有的文章、图片、音频视频文件等资料的版权归版权所有人所有,本站采用的非本站原创文章及图片等内容无法一一联系确认版权者。如果本网所选内容的文章作者及编辑认为其作品不宜公开自由传播,或不应无偿使用,请及时通过电子邮件或电话通知我们,以迅速采取适当措施,避免给双方造成不必要的经济损失。
论坛活动 E手掌握
微信扫一扫加关注
论坛活动 E手掌握
芯片资讯 锐利解读
微信扫一扫加关注
芯片资讯 锐利解读
推荐阅读
全部
输入
频率

小广播

独家专题更多

富士通铁电随机存储器FRAM主题展馆
富士通铁电随机存储器FRAM主题展馆
馆内包含了 纵览FRAM、独立FRAM存储器专区、FRAM内置LSI专区三大部分内容。 
走,跟Molex一起去看《中国电子消费品趋势》!
走,跟Molex一起去看《中国电子消费品趋势》!
 
带你走进LED王国——Microchip LED应用专题
带你走进LED王国——Microchip LED应用专题
 
电子工程世界版权所有 京ICP证060456号 京ICP备10001474号 电信业务审批[2006]字第258号函 京公海网安备110108001534 Copyright © 2005-2016 EEWORLD.com.cn, Inc. All rights reserved