By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.
This reference design provides a power-supply circuit with an input voltage of 3.3V, an output voltage of 1.8V, and an output current of 1A using the MAX8869 low-dropout linear regulator. The circuit was developed to power a MGTVCCAUX rail on a Xilinx® Kintex® Ultrascale™ FPGA. Included in this reference design are a schematic and a bill of materials.
This reference design provides a power-supply circuit with an input voltage of 10.8V to 13.2V, an output voltage of 1.80V, and an output current of 2A using the MAX15303 InTune™ Point-of-Load (PoL) Controller. The circuit was developed to power a VCC1V8 rail on a Xilinx® Kintex® Ultrascale™ FPGA. Included in this reference design are a schematic, applications information, and a bill of materials.